1. Field of the Invention
The present invention relates to a semiconductor device with loop pattern structure and a method of fabricating the same, which only needs an alternating phase shift mask (alt-psm) with single exposure process. The alternating phase shift mask used for fabricating the same is also disclosed.
2. Description of the Related Art
Recently, phase shift technologies, instead of conventional chrome-on-glass (COG) technologies, have been incorporated into the design-to-silicon flow, allowing consistent and reliable reduction of IC feature size and providing a significant improvement in chip performance. As well, smaller feature size for ICs is less costly.
FIG. 1 is a schematic diagram of a conventional COG technology. FIG. 2 is a schematic diagram of an alternating phase shift technology. As shown in FIG. 1, the COG technology uses binary mask, while the alternating phase-shift technology uses alternating phase shift mask (alt-psm), as shown in FIG. 2, having a neighboring pattern with 180xc2x0 phase difference to produce a negative step waveform (of field amplitude). Thus, such a phase difference on an alt-psm leads to destructive interference of impinging light, thereby eliminating light exposure intensity between two patterns and obtaining higher resolution. Neighboring line pattern layouts with 180xc2x0 phase difference such as an example of a memory cell layout shown in FIG. 3 are thus produced. Blank or white regions are clear or transparent for light to transmit through, and are denoted as either 180xc2x0 or 0xc2x0 to represent the phase differences when light passes through them. Regions with slashes are opaque to block light passing therethrough.
However, manufacturing semiconductor products by using an alt-psm is expensive and with low throughput. Additionally, phase conflict (indicated by a circle in FIG. 3) inevitably occurs at phase edges 30 between alt-psm region 10 (with 180xc2x0 phase difference) and non-psm region 20 (with 0xc2x0 phase difference), for example active area structure and/or gate conductor structure, and affects printed features in lithography. Due to destructive interference, an alt-psm region 10 and an adjacent non-psm region 20 always render an almost 0 light intensity region on an exposed subject no matter an opaque region exists between them or not. In FIG. 3 (an alt-psm), region 30 is blank and should refer to an uniformly-exposed region on an exposed subject. However, since an alt-psm region 10 and an adjacent non-psm region 20 adjoin each other in region 30, there is somehow a 0 light intensity region on an exposed subject, creating unwanted images. The unwanted images are currently erased by a trim mask (described in U.S. Pat. No. 5,538,833). However, such an optical lithography requires double exposure (because of the need of an alt-psm and a trim mask), leading to design complexity, difficulty in defect inspection and repair, and layout impact driven by the required trim at high resolutions.
Accordingly, the object of the present invention is to provide a semiconductor device with loop line pattern structure, which only needs an alternating phase shift mask with single exposure to save the process cost.
The present invention provides an alternating phase shift mask with dark loops thereon, a memory array fabricated with the alternating phase shift mask, and a method of fabricating the memory. The dark loops always separate first regions with 180xc2x0 phase difference from second regions with 0xc2x0 phase difference. By using the alternating phase shift mask to pattern gate-lines or active areas in a DRAM array, no unwanted image is created in the DRAM array and only one exposure is needed to achieve high resolution requirement.